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The article titled “Hardware-efficient quantum error correction via concatenated bosonic qubits” presents a significant advancement in quantum computing by demonstrating a scalable and hardware-efficient approach to quantum error correction (QEC). The research focuses on reducing the physical-qubit overhead associated with error correction, which is a major challenge in realizing practical quantum computers. The authors achieve this by using a superconducting quantum circuit to implement a logical qubit memory based on concatenated bosonic cat qubits and an outer repetition code. Below is a detailed summary of the key points and findings from the article.

Introduction and Background

Quantum computers hold the promise of solving complex problems in fields such as materials design, quantum chemistry, and cryptography. However, to achieve practical quantum computation, quantum error correction (QEC) is essential. QEC involves encoding a logical qubit redundantly across many noisy physical qubits to protect against errors. The challenge lies in the large physical-qubit overhead required for error correction, which motivates the search for more hardware-efficient approaches.

The authors propose a solution using bosonic qubits, which encode qubit states in the infinite-dimensional Hilbert space of a quantum harmonic oscillator. Bosonic QEC leverages the large Hilbert space to suppress errors, and experiments have demonstrated this using cat codes, binomial codes, and GKP codes. The authors build on this by concatenating bosonic QEC with an outer repetition code, which reduces the resource overhead for error correction.

Key Contributions

Concatenated Bosonic Codes: The authors demonstrate a logical qubit memory using a concatenated bosonic code. The inner code is a cat qubit, which natively suppresses bit-flip errors, while the outer code is a repetition code that corrects phase-flip errors. This approach reduces the physical-qubit overhead compared to traditional QEC codes like the surface code.
Noise-Biased CX Gates: The authors implement a noise-biased controlled-X (CX) gate between a data cat qubit and an ancilla transmon qubit. This gate minimizes undesired bit flips on the cat qubit caused by ancilla errors, which is crucial for maintaining the noise bias of the system.
Experimental Setup: The experiment is performed using a superconducting quantum circuit with five bosonic modes (data qubits) and four ancilla transmons. The bosonic modes are coplanar waveguide resonators with long coherence times (T1 > 60 μs, T2 > 80 μs). The ancilla transmons are used for syndrome measurements to detect and correct phase-flip errors.
Error Correction Performance: The authors measure the logical error rates for both bit-flip and phase-flip errors. The logical bit-flip error is suppressed by increasing the cat qubit mean photon number, while the phase-flip error is corrected using the repetition code. The minimum measured logical error per cycle is 1.75(2)% for the distance-3 code and 1.65(3)% for the distance-5 code.

Detailed Methodology

1. Quantum Device and Circuit Design

The quantum device consists of five bosonic modes (data qubits) and four ancilla transmons. The bosonic modes are stabilized using two-photon dissipation, which confines the qubit states to the |±α⟩ manifold, where |α⟩ and |-α⟩ are coherent states. This stabilization exponentially suppresses bit-flip errors as the mean photon number |α|² increases.

The ancilla transmons are used to measure the stabilizers of the repetition code, which detect phase-flip errors. The stabilizers are measured using CX gates between the ancilla and data qubits. The authors implement a noise-biased CX gate by encoding the ancilla qubit in the states |0⟩ = |g⟩ and |1⟩ = |f⟩, where |g⟩, |e⟩, and |f⟩ are the lowest three energy eigenstates of the transmon. This encoding ensures that the dominant ancilla decay events (|f⟩ → |e⟩ and |e⟩ → |g⟩) do not cause bit-flip errors on the cat qubit.

2. Noise-Biased CX Gate

The noise-biased CX gate is a critical component of the error correction scheme. The gate is implemented using a tunable dispersive coupling between the ancilla transmon and the storage mode (cat qubit). The authors demonstrate that the gate is robust against ancilla decay events, which is essential for maintaining the noise bias of the system. The performance of the CX gate is characterized by measuring the bit-flip and phase-flip times of the cat qubit during repeated CX gate cycles.

3. Error Correction and Decoding

The authors perform error correction by repeatedly measuring the stabilizers of the repetition code. The stabilizers are measured using a sequence of CX gates, ancilla readout, and reset. The syndrome measurements are decoded using minimum-weight perfect matching (MWPM), a standard algorithm for error correction in QEC codes.

The authors also make use of erasure errors, which occur when the ancilla transmon decays from the |f⟩ state to the |e⟩ state. These erasures are detectable and can be accounted for in the decoding process, reducing the effective syndrome measurement error.

4. Logical Error Rates

The authors measure the logical error rates for both bit-flip and phase-flip errors. The logical bit-flip error is passively suppressed by the cat qubit encoding, while the logical phase-flip error is corrected using the repetition code. The authors find that the logical phase-flip error rate increases with the cat qubit mean photon number |α|², as expected, but the distance-5 code outperforms the distance-3 code, indicating that the physical phase-flip error rates are below the error threshold of the repetition code.

The logical bit-flip error rate decreases with increasing |α|², as the cat qubit encoding provides stronger protection against bit-flip errors. The authors achieve sub-1% logical bit-flip error rates for the distance-5 code at |α|² = 4.

Results and Discussion

The authors demonstrate that the concatenated bosonic code achieves comparable logical error rates for both distance-3 and distance-5 codes, despite the increased number of fault locations in the distance-5 code. This is due to the high degree of noise bias preserved during error correction.

The key findings are:

The logical phase-flip error rate scales as |α|²^γ, where γ is the scaling exponent. The authors measure γ = 1.63 ± 0.04 and γ = 1.86 ± 0.03 for the distance-3 code sections, and γ = 2.31 ± 0.02 for the distance-5 code. This indicates that the increased code distance provides greater resiliency to phase-flip errors.
The logical bit-flip error rate decreases with increasing |α|², reaching below 0.5% for the distance-3 code and below 1% for the distance-5 code at |α|² = 4.
The overall logical error per cycle is minimized at |α|² ≈ 1.5, where the bit-flip and phase-flip contributions are comparable. The best-measured performance for the distance-5 code is 1.65 ± 0.03% at |α|² = 1.5.

Error Budget and Future Improvements

The authors provide an error budget for the distance-5 repetition code, breaking down the contributions from different error mechanisms:

Cat intrinsic bit-flip errors: These dominate at small |α|².
CX-gate-induced bit-flip errors: These also contribute at small |α|².
Cat intrinsic phase-flip errors: These dominate at large |α|².
Syndrome measurement errors: These contribute at all |α|².

The authors project that by optimizing the cycle time and using improved cat qubit circuits, the overall logical error per cycle could be reduced to 0.5% with a distance-5 code. Further improvements in ancilla lifetimes and coherence times could enable even lower logical error rates.

Conclusion and Outlook

The authors conclude that concatenated bosonic codes are a promising approach for achieving hardware-efficient quantum error correction. The use of noise-biased qubits and low-overhead repetition codes enables scalable and fault-tolerant quantum computation. The authors highlight several directions for future research, including:

Improving ancilla lifetimes: Longer ancilla lifetimes would reduce the probability of ancilla-induced bit-flip errors.
Using cat qubits as ancillas: This could eliminate the need for transmons and further reduce errors.
Concatenating with surface codes: This could provide additional protection against bit-flip errors and improve hardware efficiency.

The authors also project that with improved coherence times and bit-flip suppression, logical error rates as low as 10^-8 could be achieved, making concatenated bosonic codes a compelling candidate for practical quantum computing.

Significance

This work represents a significant step forward in the development of hardware-efficient quantum error correction. By leveraging the intrinsic error suppression of bosonic qubits and the low overhead of repetition codes, the authors demonstrate a scalable approach to fault-tolerant quantum computation. The results suggest that concatenated bosonic codes could play a key role in realizing practical quantum computers capable of solving complex problems in science and technology.

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